Provably good performance-driven global routing

Provably good performance-driven global routing

We propose a provably good performance-driven global routing algorithm for both cell-based and building-block design. The approach is based on a new bounded-radius minimum routing tree formulation. We first present several heuristics with good performance, based on an analog of Prim's minimum spanning tree construction. Next, we give an algorithm which simultaneously minimizes both routing cost...

Provably good moat routing

Moat routing is the routing of nets between the input/output pads and the core circuit. In this paper, it is proved that moat routing is NP-complete under the routing model in which there are no vertical con icts and doglegs are disallowed (i.e., every net is routed within a single track). This contrasts with the fact that channel routing is e ciently solvable under these restrictions. The pape...

Performance Driven Global Routing Through Gradual Refinement

Performance Driven Global Routing Through Gradual Re nement

We propose a heuristic for VLSI interconnect global routing that can optimize routing congestion delay and number of bends which are often competing objectives Routing exibilities under timing constraints are obtained and exploited to reduce congestion subject to timing constraints The wire routes are determined through gradual re nement according to probabilistic estimation on congestions so t...

Provably good global buffering by generalized multiterminalmulticommodity flow approximation

To implement high-performance global interconnect without impacting the placement and performance of existing blocks, the use of buffer blocks is becoming increasingly popular in structured-custom and block-based ASIC methodologies. Recent works by Cong, Kong, and Pan [5] and Tang and Wong [21] give algorithms to solve the buffer block planning problem. In this paper, we address the problem of ...